Field of the Invention
The present invention relates to a chip accommodation tray for accommodating semiconductor chips or the like that have been diced by a dicing saw of a cutting apparatus or the like.
Description of the Related Art
In a semiconductor device fabrication process, it has been customary to form devices such as integrated circuits (ICs) and large scale integrations (LSIs), in a multiplicity of areas arranged in a grid pattern on the surface of a substantially disk-shaped semiconductor wafer, and cut the semiconductor wafer along projected dicing lines demarcating the areas with the devices formed therein into individual semiconductor chips. The semiconductor chips thus divided are then packaged and widely used in electric devices including mobile phones and personal computers.
There have been demands for lighter and smaller electric devices including mobile phones and personal computers, and packaging technologies have been developed to produce smaller packages to be used for packaging semiconductor chips, referred to as chip-size packages (CSP). One type of CSP that has been put to practical use is called Quad Flat Non-lead (QFN) package. The QFN packages are produced as follows: A plurality of semiconductor chips are arranged in a matrix on a metal plate such as a copper plate which includes a plurality of connection terminals corresponding to the connection terminals of the semiconductor chips and a plurality of projected dicing lines formed in a grid pattern to demarcate the metal plate into areas so as to be aligned with the semiconductor chips, respectively. The metal plate and the semiconductor chips are integrally combined with each other by a resin layer molded on the reverse sides of the semiconductor chips, thereby producing a CSP board as a package board. The package board is then cut along the projected dicing lines into individually packaged chip-size packages.
The package board is cut generally by a cutting apparatus having a cutting blade. The cutting apparatus is provided with a jig that has, in regions corresponding to the projected dicing lines, clearance grooves formed in a grid pattern for clearing the cutting edge of the cutting blade, and has suction holes provided respectively in a plurality areas demarcated by the clearance grooves. The package board is held under suction by the jig that has been positioned on a holding table, and while the cutting blade is rotating, the holding table is moved relatively to the package board along the projected dicing lines on the package board, cutting the package board along the projected dicing lines into individual chip-size packages. Thereafter, the divided individual chip-size packages are accommodated in a chip accommodation tray having a plurality of accommodation compartments, and then transported to an assembling step (see, for example, Japanese Patent Laid-open No. 2001-239365).